1. Field of the Invention
This invention relates to clock and data recovery circuits and, more particularly, to techniques for clock and data recovery.
2. Description of the Related Art
High-speed data communication systems frequently rely on clock and data recovery (CDR) circuits within the receiver instead of transmitting a reference clock with the data. For example, serial data communications may include the use of serializer-deserializer (SERDES) elements at each end of a communications link. Within a SERDES, a CDR may extract a clock that is embedded in the incoming data stream. Once a clock is recovered, it is used to sample the incoming data stream to recover the individual bits. A variety of clock recovery circuits are well known, including phase-locked loops (both analog and digital) and delay lock loops. Regardless of the circuit used, a clock recovery circuit attempts to extract the frequency and phase of the clock from a data stream.
During propagation, data signals may experience distortion due to bandwidth limitations, dispersion, etc. in the communication channel. These effects cause a spreading of signal pulse energy from one symbol period to another. The resulting distortion is known as inter-symbol interference (ISI). Generally speaking, ISI becomes worse as the speed of communication increases. As a result, high-speed communication systems often incorporate circuitry to equalize the effects of ISI. One technique for reducing the effect of ISI is to use a Finite Impulse Response (FIR) filter in the transmitter to equalize the signal before transmitting it through the communication channel. Various parameters of the FIR determine the effect the FIR has on the signal. Various properties of the communications channel determine the appropriate settings of these FIR parameters. For example, signals passing through a communication channel may be affected by electrical properties as well as the temperature and humidity of the channel. Some of these properties may vary during operation, suggesting a need to vary FIR parameters during operation to maintain proper ISI equalization, particularly at high communication speeds.
Another equalization technique involves using a decision feedback equalizer (DFE) in the receiver. DFE's produce an equalized data stream as follows. A clock recovered from the data is used to sample the data at regular intervals. The output of the sampler, which constitutes the retimed data, is stored in a series of latches. The input of the sampler includes the original data plus the individually weighted outputs from each latch. The weights are determined adaptively by analyzing the resulting data stream. Over time, the DFE is expected to produce a stable set of weights that equalize ISI. In order to function properly, the DFE requires a stable recovered clock.
To recover a stable clock, one type of CDR uses an algorithm known as the Muller-Mueller algorithm. Performance of the Muller-Mueller algorithm is improved if the received signal is equalized before being sampled. There are multiple approaches to equalization and CDR adaptation. One approach is edge-based sampling of a received data signal. In edge-based sampling, the received data signal is sampled at a time when the data is transitioning between bits. Edge-based sampling is often preferred for CDR adaptation. Unfortunately, edge-based sampling techniques generally increase the number of samples that must be taken in each cycle. More sampling per cycle increases the circuitry required and the power consumption of SERDES elements. Another error-monitoring approach is symbol-based sampling in which samples may be taken at a time when the data is not transitioning between bits, i.e. in mid-symbol. Mid-symbol sampling may be preferred for DFE and FIR adaptation. Unfortunately, most current error-monitoring implementations require both mid-symbol and edge-based sampling, increasing circuitry and power consumption in a SERDES. Alternatively, protocol-specific adaptation may be achieved by sending a special pattern of bits through the communications link that is used to tune the CDR and DFE elements. Unfortunately, these techniques only adapt the link for specific communications protocols.
In addition to the above considerations, during adaptation, CDR, DFE, and FIR elements may interact with each other, complicating the process of achieving optimal settings. In view of the above considerations, what are needed are systems and methods of efficiently adapting equalization values of FIR, DFE, and CDR parameters.